duodecaport

This document provides a preliminary description of duodecaport, a standardized I/O pinout for GPIO, microcontrollers, and FPGAs

Digilent 6 pin (4 bit) interfaces

This information is to facillitate adapter boards. 1 duodecaport can drive 3 digilent ports. Particularly since I am already using their JTAG pinout.

Old PIA devices

6522

6820

6821 8 bits + 2 bits

Z8536

82C55

MC68901

Z80-PIO

Z80-PIO

Strobed Data Notes:

To allow two strobed ports to be connected together using 1:1 wiring, it should be possible to swap the strobe and ack pins.

Separate clock and strobe signals were defined to allow synchronous use with the host FPGA/GPIO port providing a steady clock signal. Need to define a modified version for async operation.

82C55 Notes

8255 pinouts are included for comparison. However, this chip design is so badly broken that it's use with duodecaport is extremely limited. It lacks data direction on individual pins, direction can be set only for PA and PB on byte boundaries and port C on nibble boundaries. About the only aspect of this chip that was well thought out was the use of 8 bits data plus 4 handshake, but they weren't even consistent about taking handshake signals from the correct nibble of port C.

65C22 VIA notes

The 6522 VIA provided 8 data lines plus 2 handshake lines on each of two ports. Each line was independently programmable as input or output. To connect a 6522 to duodecport, connect all 4 handshaking signals to each port. CA2 and CB2, can provide a pulse when data is output or when input is accepted. CA1/CB1 can provide an output that goes low when data is output to the corresponding port and stays low until there is an acknowledge pulse on CA2/CB2. CB2 also functions an SPI data line and CB1 as a SPI clock line.

HCS12

Many of the port pinouts are partially based on the freescale MC9S12DP256 board I designed. It connects one full port and one half port to each I/O. So, for example, a dual SPI port is split in half to provide the four handshaking lines for two doudecaports.

Misc Chips

• National DP8348C PHYTER Single Port 10/100Mb/s Etherenet PHY transceiver MII/RMII
• SMSC CirCC - 16C550A uart with IRDA, Consumer IR, etc.

USB Low Pincount Interface (ULPI) Notes:

ULPI defines a 12 line (8 data bit) or 8 line (4 data bit, double pumped) interface between a USB transceiver and a USB controller which supports 480Mbps USB high speed mode. The PHY (transceiver) provides a 60MHz clock signal. Lower speed buses can use a transceiver with a single transmit and receive pin although the overhead signals add many additional pins. Curiously, the standard also describes a Carkit mode which is used to carry USB, UART, or Audio data over the same lines. Carkit spec is $125 frrom CEA.

• SMSC USB3300 USB Low Pin Interface (ULPI) Supports USB on the Go, can be host or device port. Does not support DDR. Supports On-the-go session request protocol (SRP) and Host Negotiation Protocol (HNP)
  http://www.smsc.com/main/datasheets/3300.pdf
• Philips ISP1504/ISP1505/ISP1506 are ulpi interface PHYs.
  Only the 1505 supports SRP and it uses 1.8V I/O only.
• http://www.nxp.com/pip/isp1109/ 12Mbps USB interface with Carkit (not ULPI, high pin count)
• http://www.ulpi.org/documents.html
• http://en.wikipedia.org/wiki/CEA-936-A
• MC13890 includes power and audio control and a USB transceiver (not ULPI) with carkit interface. BGA package but it is a sparse matrix like they were actually thinking about pcb layout using two signal layers.

PCI express and PXPIPE

PCI express is a high speed 2.5Gbps serial version of PCI. One lane in each direction, expandable to 2/4/8/16. PXPIPE is a parallel (8 data + clock in each direction) interface to a few PCI-e SERDES chips. A single pair is used in each direction for 1 lane PCI-e and can be up to 1 Meter long with approx 100 ohm termination (depends on trace impedence, typ 50 ohm each). PCI express uses 8B/10B encoding and is self clocking. Usually, Video cards are 16x (r 8x for two video cards) and other cards are 1x. Credit based flow control. There is a considerable overhead on each packet of 24 to 32 bytes and payload can be from 0-4096 bytes. 250MB/s throughput in each direction (500MB/s total). Interrupts are passed as messages. In addition to the standard PC slot, there are ExpressCard (replaces PCMCIA/Cardbus), Mini PCI Express (notebook internal, 51x30mm), CompactPCIxpress (replaces CompactPCI eurocard format), and IPCI-E (industrial, PCI express on passive ISA backplane format). PCIe switches (www.plxtech.com is one source) allow multiple masters or slaves to be connected to a PCIe channel.

http://www.interfacebus.com/Design_Connector_PCI_Express.html

Access to PCI Express specification requires $3000 PCISIG membership. There is a book which is a cheaper source of info:

http://www.amazon.com/PCI-Express-System-Architecture-Anderson/dp/0321156307/

(includes a substantial preview).

• Phillips (now called NXP) PX1011A PCI Express PIPE (PXPIPE), Data on the FPGA side of the interface is 250Mhz 8 bit parallel. On the bus side, it is 2.5Ghz 10b/8b serial. PX1011A/PX1012A chips. BGA package , 2.%V SSTL_2 logic levels. $11.33 at digikey. Note that most of the I/O pins are on the outer 1 or 2 rows, with the exception of 3 JTAG lines, so this doesn't require lots of layers but it will still require at least a toaster oven or two heat guns to solder and inspection is difficult (maybe borrow the use of your dentists X-ray machine?).

Note that a CPLD can be used to convert double pumped PXPIPE into PXPIPE, cutting the number of FPGA pins needed from 18 down to 10.

Presentation on tight vs loose coupling of PCIe differential pairs:

http://www.plxtech.com/pdf/technical/expresslane/Tight_Coupling_Slides.pdf

Hard drive interfacing

At this point, efficient interfaces to a hard drive are a bit of a problem as hard drives interfaces tend to have either very high pin counts or data rates which are too fast for programmable logic.

It would take at least two ports to connect directly to an IDE interface. Other options include using a CPLD to connect to a single port or to use an IDE controller with an 8 bit multiplexed address/data bus (if availible).

Required signals: D0-D15, CS0, CS1, DIOR, DIOW

Signals which can be ignored or tied to a level: CD1/CD2 (PCMCIA only), DMARQ, DMACK, IORDY, CSEL, PDIAG/CBLID

Optional INTRQ, RESET1

At this point, connecting hard drives (if 8GB flash cards won't do) to an embedded design might be best done through IDE, IDE to SATA bridge, USB to IDE/SATA bridge, PCI Express to SATA bridge, a SATA host controller, PXPIPE to PCI-e to SATA, LPC bus to ISA to IDE, etc.

SERDES

A number of high speed serial busses such as PCI Express, SATA, fiberchannel, etc. use 8b10b SERDES (serializer/deserializer).

While some high end FPGAs have generic SERDES I/Os, the development tools for these chips are expensive. So I am looking for some universal serdes chips. Found a chip for PXPIPE.

88i8030 is a SATA compatible SERDES to PATA bridge.

PMC Siera QuadPHY 6G SERDES is apparently Fiber Channel, iSCSI, STA, SAS, PCI express, and infiniband. $250 each when released.

FPGA to FPGA links

There are a number of options for FPGA to FPGA links. Here, I am concerned with links that connect the internal busses together rather than connecting a simple stream of data.

• PXPIPE (parallel version of PCI express used by some converter chips) on two duodecaports, one for each direction.
• Double pumped PXPIPE on a single duodecaport
• LPC bus on a single duodecaport
• Multiplexed address/data port.
• RMII (ethernet PHY interface)
• ULPI (USB PHY Low Pin count Interface)

Options include:

• Using two doudecports to double the width and effective data rate
• Double pumping to double the data rate without increasing the number of wires
• Double pumping and using LVDS to make the signals more robust without changing the number of wires. May increase data rate over longer wires.

I would like to design a generic bus interface module (master and/or slave) that uses the same set of wires to implement different busses in a common way. This would actually be a good IP core to include in ASIC or dedicated silicon designs as it would allow the same part to be used on a variety of different buses. Although a few of the faster busses can't be implemented on cheaper FPGAs, an expanded version of the core for ASICs could allow PCI, ISA, LPC bus, PXPIPE, multiplexed address/data, and possibly SATA, PCI-e, USB, or Firewire to be used over the same pins with a few extra pins, wire bonds, or JTAG bits selecting the bus interface.

Low Pin Count Bus (LPCbus)

This is a bus defined by intel to eliminate ISA on motherboards to connect to lower speed legacy I/O devices such as keyboard, mouse, serial, parallel, and floppy disk ports. Address, data, and commands are multiplexed over a 4 bit wide interface at 33Mhz. Because of the higher data rate, it is slightly faster than ISA.

http://www.intel.com/design/chipsets/industry/lpc.htm

Required Signals: LAD[3:0], LFARME#, LRESET#, LCLK

Optional Signals: LDRQ#, SERIRQ, CLKRUN#, LPME#, LPCD#, LSMI#

An example chip (not carried by digikey) is the SMSC LPC47N267 super I/O which has 2 16C550 serial, Paralle Port, some GPIO lines, Floppy disk controller, and X-bus. Digikey search of Super I/O, however turns up some other LPC parts

This bus looks well suited to adding a lot of legacy ports to an FPGA based system. Some super I/O ports have as many as 6 serial I/O ports. Some have IRDA/SIR/FIR, RTC, Game port, MIDI, Fan control, GPIO and/or watch dog timer. There are also LPC to ISA bridges.

LPC was part of the ISA to PCI transition but is also used in embedded systems. At least some Geode processors support LPC. In some cases USB may have supplanted LPC. However all USB to serial adapters are defective with respect to XON/XOFF flow control to devices with small buffers or which must pause serial activity while doing other work (such as burning flash).

The winbond W82L518D is an LPC to memory card interface (SD Card, Memory Stick, Smart card)

LPC was apparently used for some docking station interfaces, as well.

The winbond W49V002A is a 256Kx8 3.3V flash memory with LPC interface. The SST49LF020 is also a 256Kx8 LPC flash. Sandisk apparently has some diskonchip models that support LPC.

SMSC, Winbond, and National make Super I/O devices.

LPC interface I/O cards will be intended for FPGA use. They can also be used with microcontrollers, etc. but speed will be slower as the bus will have to be bit banged.

http://warmcat.com/milksop/cheapLPC.html

Someones ABEL file to interface SRAM on LPC bus http://www.j-rex.com/assets/download/lpc_sram.abl

Connector orientation

Microcontroller/FPGA boards should have the ground pins oriented away from the edge of the card. The reason for this is that these cards will normally be double or multilayer cards which can have lines between pads but the I/O cards, which may be home etched prototypes, benefit from having ground at the edge of the card.

An exception to this is if right angle connectors are used on both the FPGA/microcontroller and I/O cards. However, the prefered configuration is to use vertical male on top female on bottom cards which facilitate stacking multiple cards on the same I/O connector and facilitate logic analyzer, oscilliscope, and other test probe access. This also facilitates embedding the microcontroller/FPGA card layout directly into a larger board after prototyping.

A standardized spacing will be defined for pairs of duodecaports to facilitate direct stacking of I/O modules that require more than one port. Currently, it looks like that spacing will be 1.550” from pin1 to pin1.

Standard card size is looking like it will probably be:

Width: 1.5” (38.1 mm)

Length: 100mm (3.937), some cards will be less than full length.

This lets a eurocard be split into four cards with a 100 mil (2.54mm) kerf.

Panel Size:

DSS 160x100mm 4

DSQ 320x200mm 16

10x14: 24

5.5x4: 3

11x8: 14

Memory notes

Memory interfaces tend to use up I/O pins like crazy. And newer DRAM doesn't share a bus well with flash and other devices. This is why I am looking at a two port wide, double pumped multiplexed address data bus. Multiplexing the address with the data will add one clock cycle overhead to each non-sequential memory burst which is a small price to pay for not using up half your FPGA pins.

Xilinx is coming out with a device with over 1MB of flash on the FPGA soon.

New Microcontroller designs

For new microcontroller board designs, the use of an FPGA or CPLD is recommended instead of existing GPIO chips. This is much more flexible and can be cost competitive.

New GPIO designs

I am working on a GPIO design that would be compatible with the pinout and much of the functionality described here. It will initially be implemented in an FPGA. (Note: add keyboard wakeup option on all pins).

I/O cards

This bus is being designed to work with a variety of modules

• LCD display module
• LED display module
• breadboard adapter (14 pin sip)
• dip switch, pushbutton switch
• stepper driver
• Full bridge servo driver with optical encoder feedback
  (Servo loop to be completed in FPGA)
• Ethernet RMII (FPGA only)
• ULPC 480Mbps USB Transceiver (FPGA only), with dual connectors for use as a USB protocol analyzer
• RS-232 transceiver
• RS-422/485 transceiver
• Slow speed analog I/O
• High speed analog in
  For oscilliscope, software defined radio, and video work
• High speed analog out
• PCI express (FPGA only)
• memory boards
• Universal eprom/eeprom/flash/MCU programmer
• ATE modules
• level translation module, high speed bidirectional
• level translation module, lower speed, high voltage
• aircraft servo module
• JTAG module
• MMC/SD Card/SDIO module
• High speed FPGA to FPGA interconnects for multiple FPGA designs
• ARM CPU for hybrid FPGA/Microcontroller designs
• IDE/ATAPI
• logic analyzer probes
• isolated RS-232/422/485
• LPC to ISA and/or PC-104 bridge
• LPC super I/O (serial/parallel/floppy/keyboard/mouse)
• SATA?
• Firewire?
• IDE controller?
• Ethernet MAC (for microcontroller or FPGA)
• dual duodecaport PXPIPE to PCI express to PCI bridge
• duodecaport to CPLD to duodecaport
• USB to duodecaport
• PC Parallel to duodecaport
• SD card to duodecaport for PDAs.
• VGA and/or DVI
• LPC to ISA to IDE
• Camera sensor
• Linear image sensor (as used in scanners)
• Environmental sensors: accelerometers, tilt, compass, pressure, temperature, humidity, gas detectors, etc?
• WiFi, bluetooth, zigbee, GPS?
• Direct connection module. Connect a port on the FGPA/micro to an I/O device using a small PCB with two stacking connectors instead of a ribbon cable. Gives access to signals for testing purposes.
• magstripe, barcode, RFID?
• IrDA, SIR, FIR, CIR
• compact flash/pcmcia? Compact flash and PCMCIA (but not cardbus) are electrically similar to the ISA bus so an LPC to ISA bridge could be used. Note that some slots are 5V and others are 3.3V or dual voltage. Note that different pinouts
  are used in memory/I/O/ and IDE modes
• opto-22 module
• DSP
• User interface board (LCD, joystick, etc).
• Multiple MMC/SD/SDIO module. SPI only. 3V only. Can be used for compact sensor cards, etc.

The plan is for most of the I/O cards to have CPLDs on board. These will allow the same board to be used with alternative interfaces including split SPI, SPI with 8 chip selects, non-standard SPI from various microcontrollers, Parallel interface, etc. CPLDs will also help with level translation, pin count reduction, and buffering. Even trivial cards such as a card with 12 LEDs

will use CPLDs instead of CMOS buffers.

Firewire (IEEE-1394)

TI TSB11LV01 is a 100Mbps firewire PHY. Looks like 9 essential I/O pins. Digikey non-stock, large minimum order.

TSB41AB1PAP is a 100/200/400Mbps firewire PHY. Looks like 10 to 16 pin link interface, depending on speed. However, the

data is single pumped so double pumping could be used to lower pin count with a CPLD. $3.38 at digikey.

3 port PHYs also availible.

Ethernet

National DP83848 is a single port 3.3V MII/RMII interfac6e PHY.

National DP83848 3.3V, 10/100Mb/s, JTAG MII or RMII interface, digikey $4.73, external 50Mhz XTAL oscillator for RMII mode, 48 pin LQFP (7mm x 7mm).

TI TLK2201 2.5V (3.3V tolerant), gigabit ethernet transceiver, higher pin count interface.

SMSC LAN91C96 is a Non-PCI single chip ethernet MAC, 10Mbps only

Magjack jacks contain magnetics inside connector.

3 port PHYs also availible.

Multiplexed Address Data bus

Only a single bus master is supported.

Can use one or two dodecaports. The normal mode is one. 8 bit data transfers per clock cycle in single pumped mode and 16 bit in double pumped. 8/16/32/64 bit addresses are supported, by simply strobing the address line multiple times and sending out data in little endian order. The same number of address bytes need to be used when addressing a specific device but not all devices need to use the same number of bytes. The top 3 or 4 bits are used for the device address. In double pumped mode, the bytes are sent out two per clock cycle. Single and double pumped devices can be mixed. Data or address is transferred on the rising edge of the clock for single pumped and on the falling and rising edges (in that order) for double. Each device looks at the last address transferred on the rising edge to determine if it is selected. To address a device with 16 bit wide registers in single pumped mode, the device will be responsible for buffering the bytes written to the lower byte address and then using them when the upper address is written. A single 8/16 bit conversion latch register can be shared across multiple device registers. Autoincrement of addresses can be supported for burst transfers without the overhead of clocking out an address on each cycle.

Interrupts and reset are somewhat limited by the number of pins for a single port implementation. Reset may be accomplished by writing to a register. Interrupts may be polled or one of the data lines can be driven through a resistor with the bus tristated when not in use. This requires that the master insert enough idle cycles to sample the interrupt lines. The possibility of asserting both the address strobe and data strobe will be looked into as an alternative means of sampling interrupts, with R/W being used as an extra signal to allow extra bus control signals (including perhaps device reset). Address strobe + datastrobe + write = reset (needs to be deglitched), address strobe + datastrobe + read = sample interrupts/dma requests. With appropriate signal levels and async reset, the normal pullups on an FPGA or micro could reset interface boards when master is reset.

Synchronous or async transfers may be supported.

Stacking Headers

Mil-Max SSQ-113-03-G-D is a 26 pin female header with wire wrap pins, suitable for use as a male/female stacking header ($5.33 digikey). SSQ-113-03-S-D is similar but the wire wrap pins are only tin plated instead of gold flash.

Stepper driver interface

Put 2 ohmicron connectors on each set of lines to support ganged axes.

Put DB-25 for other brands

User Interface board

• LCD (nokia)
• 4 joystick switches
• toggle switches? estop, etc.
• MMC card socket, possibly under the LCD

High speed ADC, digital oscilloscope, video in

The AD9054A is a 200MSPS 8 bit ADC. Single 100Mhz or dual 100Mhz parallel outputs. Minimum sample frequency 25Mhz. $31.80 each at digikey ($27.78 for 135Mhz version). 44-LQFP. Good bang for the buck. Minimum clock rate 1Mhz, Maximum 200Mhz. Internal reference. 1V p-p analog input. Minimum interface is 8 data bits, 1 clock, and one data strobe but that halves the operating frequency; optionally the clock can be differential.

ADC08100 is a 8 bit 20MSPS to 100MSPS converter. $8.63 digikey, 24 TSSOP. 3V operation. external reference. Analog input requires buffering.

ADC08B200CIVS ($23.40) 200MSPS with 1024 byte capture buffer, external reference. 500Mhz bandwidth. Buffer can be disabled to read outputs directly (6 cycle delay)

ADCS9888 is a 3 channel (RGB) ADC 205/170/140MSPS video ADC. $22.65 for 205Mhz version, $16.20 at digikey for 170MSPS version, $14.14 fro 140MSPS version. 75/150/300/500Mhz programable bandwidth. 3-3.6V analog supply, 2.2 to 3.6V I/O supply. 0.5V or 1V single ended input, positive going range. High impedence input. Suggest capcitive coupling for clamping and DC restoration.. 128-PQFP, not square. Double outputs for each channel. Optional 4:2:2 pulldown (driving only red and green A ports). In dual channel mode, it can support 6 inputs? It appears you get every sample in single channel mode. Series termination resistors to be used on each output. IIC access to configuration registers. Must disable horizontal sync or video inputs will be clamped. Could probably connect one set of inputs to a VGA connector and the other to BNC connectors (with hsync tied appropriately) to switch between video and scope mode. Put BNC inputs on side of the card. Or use two sets of BNC inputs, in which case I think you can digitize 6 channels at half the frequency. Will require 3 duodecaports but might be able to set it up so you only use two and hang the blue off the side, if you are only using 2/4 inputs or are using 4:2:2 pulldown. The blue pins are located appropriately for this. Could attach two cards to one FPGA, supporting a total of 6 high speed or 12 low speed channels and they would all end up on one side of enclosure, but not much room for memory. 1.3W. Internal reference. Minimum conversion rate 10 MSPS.

For software defined radio, there is a multiband filter board example here: http://wb6dhw.com/SDTCVR.html, using FST3251 (obsolete) muxes. 4-20 ohm on resistiance, 1uA leakage. Uses AD9954, AD9958/59, DACS with a cypress cy7C68013.

ADG918 is a 2GHZ 2:1 mux, unused chanels are terminated to 50 ohms (or ground for ADG919). 8-LFCSP or 8-MSOP package. $1.27 digikey. 1.65 to 2.75 power supply, only switches voltages between rails.

PXPIPE style narrow stream interface

6 lines in each direction. 4 data, double pumped. 1 clock, 1 acknowledge. The acknowledge allows it to be used with slow chips like a CPU. Output nibble, drive clock high, wait for ack to go high, output nibble, drive clock low, wait for clock to go low. If not using ack, could be used as a reset pin.

Related

Make a SD/SDIO expander for PDAs with many slots

Make a SD/MMC SPI GPIO

Make a USB to SDIO adapter