v 20040111 1
N 18400 11400 18400 9400 4
N 18400 9400 14300 9400 4
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N 11100 12100 11300 12100 4
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N 10500 12100 10600 12100 4
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N 10200 11900 10200 12400 4
N 10200 12400 14500 12400 4
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N 17100 14750 17100 15800 4
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N 12800 15700 14200 15700 4
N 14200 15900 15600 15900 4
T 15200 17300 9 5 1 0 0 0 1
pulse chip select instead of holding low
N 12800 15800 14600 15800 4
N 14600 15800 14600 15200 4
N 17000 15200 17000 16000 4
N 17000 16000 17400 16000 4
N 18600 17500 13850 17500 4
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N 13600 13700 13700 13700 4
N 13900 13700 14800 13700 4
N 17300 4000 18500 4000 4
N 17300 4200 17300 5600 4
N 17300 5600 18500 5600 4
C 10900 5300 1 0 0 EMBEDDEDMC9S12DP256.sym
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P 11900 5600 11900 5700 1 0 0
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{
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{
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{
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T 14350 7320 5 5 0 1 0 0 1
pinseq=2
T 14180 7320 5 5 1 1 0 6 1
pinlabel=SCK1/PWM2/KWP2/PP2
T 14500 7320 5 5 0 1 0 0 1
pintype=io
}
P 14300 7400 14200 7400 1 0 0
{
T 14210 7420 5 5 1 1 0 0 1
pinnumber=1
T 14350 7420 5 5 0 1 0 0 1
pinseq=1
T 14180 7420 5 5 1 1 0 6 1
pinlabel=SS1*/PWM3/KWP3/PP3
T 14500 7420 5 5 0 1 0 0 1
pintype=io
}
P 14300 7500 14200 7500 1 0 0
{
T 14210 7520 5 5 1 1 0 0 1
pinnumber=112
T 14350 7520 5 5 0 1 0 0 1
pinseq=112
T 14180 7520 5 5 1 1 0 6 1
pinlabel=MISO2/PWM4/KWP4/PP4
T 14500 7520 5 5 0 1 0 0 1
pintype=io
}
P 14300 7600 14200 7600 1 0 0
{
T 14210 7620 5 5 1 1 0 0 1
pinnumber=111
T 14350 7620 5 5 0 1 0 0 1
pinseq=111
T 14180 7620 5 5 1 1 0 6 1
pinlabel=MOSI2/PWM5/KPW5/PP5
T 14500 7620 5 5 0 1 0 0 1
pintype=io
}
P 14300 7700 14200 7700 1 0 0
{
T 14210 7720 5 5 1 1 0 0 1
pinnumber=110
T 14350 7720 5 5 0 1 0 0 1
pinseq=110
T 14180 7720 5 5 1 1 0 6 1
pinlabel=SS2*/PWM6/KWP6/PP6
T 14500 7720 5 5 0 1 0 0 1
pintype=io
}
P 14300 7800 14200 7800 1 0 0
{
T 14210 7820 5 5 1 1 0 0 1
pinnumber=109
T 14350 7820 5 5 0 1 0 0 1
pinseq=109
T 14180 7820 5 5 1 1 0 6 1
pinlabel=SCK2/PWM7/KWP7/PP7
T 14500 7820 5 5 0 1 0 0 1
pintype=io
}
P 14300 8000 14200 8000 1 0 0
{
T 14210 8020 5 5 1 1 0 0 1
pinnumber=22
T 14350 8020 5 5 0 1 0 0 1
pinseq=22
T 14180 8020 5 5 1 1 0 6 1
pinlabel=KWJ0/PJ0
T 14500 8020 5 5 0 1 0 0 1
pintype=io
}
P 14300 8100 14200 8100 1 0 0
{
T 14210 8120 5 5 1 1 0 0 1
pinnumber=21
T 14350 8120 5 5 0 1 0 0 1
pinseq=21
T 14180 8120 5 5 1 1 0 6 1
pinlabel=KWJ1/PJ1
T 14500 8120 5 5 0 1 0 0 1
pintype=io
}
P 14300 8200 14200 8200 1 0 0
{
T 14210 8220 5 5 1 1 0 0 1
pinnumber=99
T 14350 8220 5 5 0 1 0 0 1
pinseq=99
T 14180 8220 5 5 1 1 0 6 1
pinlabel=SDA/RXCAN4/JWJ6/PJ6
T 14500 8220 5 5 0 1 0 0 1
pintype=io
}
P 14300 8300 14200 8300 1 0 0
{
T 14210 8320 5 5 1 1 0 0 1
pinnumber=98
T 14350 8320 5 5 0 1 0 0 1
pinseq=98
T 14180 8320 5 5 1 1 0 6 1
pinlabel=SCL/TXCAN4/KWJ7/PJ7
T 14500 8320 5 5 0 1 0 0 1
pintype=io
}
P 14300 8500 14200 8500 1 0 0
{
T 14210 8520 5 5 1 1 0 0 1
pinnumber=105
T 14350 8520 5 5 0 1 0 0 1
pinseq=105
T 14180 8520 5 5 1 1 0 6 1
pinlabel=RXB/TXCAN0/PM0
T 14500 8520 5 5 0 1 0 0 1
pintype=io
}
P 14300 8600 14200 8600 1 0 0
{
T 14210 8620 5 5 1 1 0 0 1
pinnumber=104
T 14350 8620 5 5 0 1 0 0 1
pinseq=104
T 14180 8620 5 5 1 1 0 6 1
pinlabel=TXB/TXCAN0/PM1
T 14500 8620 5 5 0 1 0 0 1
pintype=io
}
P 14300 8700 14200 8700 1 0 0
{
T 14210 8720 5 5 1 1 0 0 1
pinnumber=103
T 14350 8720 5 5 0 1 0 0 1
pinseq=103
T 14180 8720 5 5 1 1 0 6 1
pinlabel=MISO0/RXCAN0/RXCAN1/PM2
T 14500 8720 5 5 0 1 0 0 1
pintype=io
}
P 14300 8800 14200 8800 1 0 0
{
T 14210 8820 5 5 1 1 0 0 1
pinnumber=102
T 14350 8820 5 5 0 1 0 0 1
pinseq=102
T 14180 8820 5 5 1 1 0 6 1
pinlabel=SS0/TXCAN0/TXCAN1/PM3
T 14500 8820 5 5 0 1 0 0 1
pintype=io
}
P 14300 8900 14200 8900 1 0 0
{
T 14210 8920 5 5 1 1 0 0 1
pinnumber=101
T 14350 8920 5 5 0 1 0 0 1
pinseq=101
T 14180 8920 5 5 1 1 0 6 1
pinlabel=MOSI/RXCAN4/RXCAN0/RXCAN2/PM4
T 14500 8920 5 5 0 1 0 0 1
pintype=io
}
P 14300 9000 14200 9000 1 0 0
{
T 14210 9020 5 5 1 1 0 0 1
pinnumber=100
T 14350 9020 5 5 0 1 0 0 1
pinseq=100
T 14180 9020 5 5 1 1 0 6 1
pinlabel=SCK0/TXCAN4/TXCAN0/TXCAN2/PM5
T 14500 9020 5 5 0 1 0 0 1
pintype=io
}
P 14300 9100 14200 9100 1 0 0
{
T 14210 9120 5 5 1 1 0 0 1
pinnumber=88
T 14350 9120 5 5 0 1 0 0 1
pinseq=88
T 14180 9120 5 5 1 1 0 6 1
pinlabel=RXCAN4/RXCAN3/PM6
T 14500 9120 5 5 0 1 0 0 1
pintype=io
}
P 14300 9200 14200 9200 1 0 0
{
T 14210 9220 5 5 1 1 0 0 1
pinnumber=87
T 14350 9220 5 5 0 1 0 0 1
pinseq=87
T 14180 9220 5 5 1 1 0 6 1
pinlabel=TXCAN4/TXCAN3/PM7
T 14500 9220 5 5 0 1 0 0 1
pintype=io
}
P 14300 9400 14200 9400 1 0 0
{
T 14210 9420 5 5 1 1 0 0 1
pinnumber=89
T 14350 9420 5 5 0 1 0 0 1
pinseq=89
T 14180 9420 5 5 1 1 0 6 1
pinlabel=RXD0/PS0
T 14500 9420 5 5 0 1 0 0 1
pintype=io
}
P 14300 9500 14200 9500 1 0 0
{
T 14210 9520 5 5 1 1 0 0 1
pinnumber=90
T 14350 9520 5 5 0 1 0 0 1
pinseq=90
T 14180 9520 5 5 1 1 0 6 1
pinlabel=TXD0/PS1
T 14500 9520 5 5 0 1 0 0 1
pintype=io
}
P 14300 9600 14200 9600 1 0 0
{
T 14210 9620 5 5 1 1 0 0 1
pinnumber=91
T 14350 9620 5 5 0 1 0 0 1
pinseq=91
T 14180 9620 5 5 1 1 0 6 1
pinlabel=RXD1/PS2
T 14500 9620 5 5 0 1 0 0 1
pintype=io
}
P 14300 9700 14200 9700 1 0 0
{
T 14210 9720 5 5 1 1 0 0 1
pinnumber=92
T 14350 9720 5 5 0 1 0 0 1
pinseq=92
T 14180 9720 5 5 1 1 0 6 1
pinlabel=TXD1/PS3
T 14500 9720 5 5 0 1 0 0 1
pintype=io
}
P 14300 9800 14200 9800 1 0 0
{
T 14210 9820 5 5 1 1 0 0 1
pinnumber=93
T 14350 9820 5 5 0 1 0 0 1
pinseq=93
T 14180 9820 5 5 1 1 0 6 1
pinlabel=MISO0/PS4
T 14500 9820 5 5 0 1 0 0 1
pintype=io
}
P 14300 9900 14200 9900 1 0 0
{
T 14210 9920 5 5 1 1 0 0 1
pinnumber=94
T 14350 9920 5 5 0 1 0 0 1
pinseq=94
T 14180 9920 5 5 1 1 0 6 1
pinlabel=MOSI0/PS5
T 14500 9920 5 5 0 1 0 0 1
pintype=io
}
P 14300 10000 14200 10000 1 0 0
{
T 14210 10020 5 5 1 1 0 0 1
pinnumber=95
T 14350 10020 5 5 0 1 0 0 1
pinseq=95
T 14180 10020 5 5 1 1 0 6 1
pinlabel=SCK0/PS6
T 14500 10020 5 5 0 1 0 0 1
pintype=io
}
P 14300 10100 14200 10100 1 0 0
{
T 14210 10120 5 5 1 1 0 0 1
pinnumber=96
T 14350 10120 5 5 0 1 0 0 1
pinseq=96
T 14180 10120 5 5 1 1 0 6 1
pinlabel=SS0*/PS7
T 14500 10120 5 5 0 1 0 0 1
pintype=io
}
P 14300 10300 14200 10300 1 0 0
{
T 14210 10320 5 5 1 1 0 0 1
pinnumber=9
T 14350 10320 5 5 0 1 0 0 1
pinseq=9
T 14180 10320 5 5 1 1 0 6 1
pinlabel=PT0/IOC0
T 14500 10320 5 5 0 1 0 0 1
pintype=io
}
P 14300 10400 14200 10400 1 0 0
{
T 14210 10420 5 5 1 1 0 0 1
pinnumber=10
T 14350 10420 5 5 0 1 0 0 1
pinseq=10
T 14180 10420 5 5 1 1 0 6 1
pinlabel=PT1/IOC1
T 14500 10420 5 5 0 1 0 0 1
pintype=io
}
P 14300 10500 14200 10500 1 0 0
{
T 14210 10520 5 5 1 1 0 0 1
pinnumber=11
T 14350 10520 5 5 0 1 0 0 1
pinseq=11
T 14180 10520 5 5 1 1 0 6 1
pinlabel=PT2/IOC2
T 14500 10520 5 5 0 1 0 0 1
pintype=io
}
P 14300 10600 14200 10600 1 0 0
{
T 14210 10620 5 5 1 1 0 0 1
pinnumber=12
T 14350 10620 5 5 0 1 0 0 1
pinseq=12
T 14180 10620 5 5 1 1 0 6 1
pinlabel=PT3/IOC3
T 14500 10620 5 5 0 1 0 0 1
pintype=io
}
P 14300 10700 14200 10700 1 0 0
{
T 14210 10720 5 5 1 1 0 0 1
pinnumber=15
T 14350 10720 5 5 0 1 0 0 1
pinseq=15
T 14180 10720 5 5 1 1 0 6 1
pinlabel=PT4/IOC4
T 14500 10720 5 5 0 1 0 0 1
pintype=io
}
P 14300 10800 14200 10800 1 0 0
{
T 14210 10820 5 5 1 1 0 0 1
pinnumber=16
T 14350 10820 5 5 0 1 0 0 1
pinseq=16
T 14180 10820 5 5 1 1 0 6 1
pinlabel=PT5/IOC5
T 14500 10820 5 5 0 1 0 0 1
pintype=io
}
P 14300 10900 14200 10900 1 0 0
{
T 14210 10920 5 5 1 1 0 0 1
pinnumber=17
T 14350 10920 5 5 0 1 0 0 1
pinseq=17
T 14180 10920 5 5 1 1 0 6 1
pinlabel=PT6/IOC6
T 14500 10920 5 5 0 1 0 0 1
pintype=io
}
P 14300 11000 14200 11000 1 0 0
{
T 14210 11020 5 5 1 1 0 0 1
pinnumber=18
T 14350 11020 5 5 0 1 0 0 1
pinseq=18
T 14180 11020 5 5 1 1 0 6 1
pinlabel=PT7/IOC7
T 14500 11020 5 5 0 1 0 0 1
pintype=io
}
P 14300 11200 14200 11200 1 0 0
{
T 14210 11220 5 5 1 1 0 0 1
pinnumber=8
T 14350 11220 5 5 0 1 0 0 1
pinseq=8
T 14180 11220 5 5 1 1 0 6 1
pinlabel=XADDR15/PK0
T 14500 11220 5 5 0 1 0 0 1
pintype=io
}
P 14300 11300 14200 11300 1 0 0
{
T 14210 11320 5 5 1 1 0 0 1
pinnumber=7
T 14350 11320 5 5 0 1 0 0 1
pinseq=7
T 14180 11320 5 5 1 1 0 6 1
pinlabel=XADDR14/PK1
T 14500 11320 5 5 0 1 0 0 1
pintype=io
}
P 14300 11400 14200 11400 1 0 0
{
T 14210 11420 5 5 1 1 0 0 1
pinnumber=6
T 14350 11420 5 5 0 1 0 0 1
pinseq=6
T 14180 11420 5 5 1 1 0 6 1
pinlabel=XADDR15/PK2
T 14500 11420 5 5 0 1 0 0 1
pintype=io
}
P 14300 11500 14200 11500 1 0 0
{
T 14210 11520 5 5 1 1 0 0 1
pinnumber=5
T 14350 11520 5 5 0 1 0 0 1
pinseq=5
T 14180 11520 5 5 1 1 0 6 1
pinlabel=XADDR17/PK3
T 14500 11520 5 5 0 1 0 0 1
pintype=io
}
P 14300 11600 14200 11600 1 0 0
{
T 14210 11620 5 5 1 1 0 0 1
pinnumber=20
T 14350 11620 5 5 0 1 0 0 1
pinseq=20
T 14180 11620 5 5 1 1 0 6 1
pinlabel=XADDR18/PK4
T 14500 11620 5 5 0 1 0 0 1
pintype=io
}
P 14300 11700 14200 11700 1 0 0
{
T 14210 11720 5 5 1 1 0 0 1
pinnumber=19
T 14350 11720 5 5 0 1 0 0 1
pinseq=19
T 14180 11720 5 5 1 1 0 6 1
pinlabel=XADDR19/PK5
T 14500 11720 5 5 0 1 0 0 1
pintype=io
}
P 14300 11900 14200 11900 1 0 0
{
T 14210 11920 5 5 1 1 0 0 1
pinnumber=108
T 14350 11920 5 5 0 1 0 0 1
pinseq=108
T 14180 11920 5 5 1 1 0 6 1
pinlabel=PK7/ECS*
T 14500 11920 5 5 0 1 0 0 1
pintype=io
}
P 11300 8500 11400 8500 1 0 0
{
T 11150 8520 5 5 0 1 0 0 1
pinseq=24
T 11050 8520 5 5 0 1 0 0 1
pintype=io
T 11380 8520 5 5 1 1 0 6 1
pinnumber=24
T 11420 8520 5 5 1 1 0 0 1
pinlabel=PB0/DATA0/ADDR0
}
P 11300 8600 11400 8600 1 0 0
{
T 11150 8620 5 5 0 1 0 0 1
pinseq=25
T 11050 8620 5 5 0 1 0 0 1
pintype=io
T 11380 8620 5 5 1 1 0 6 1
pinnumber=25
T 11420 8620 5 5 1 1 0 0 1
pinlabel=PB1/DATA1/ADDR1
}
P 11300 8700 11400 8700 1 0 0
{
T 11150 8720 5 5 0 1 0 0 1
pinseq=26
T 11050 8720 5 5 0 1 0 0 1
pintype=io
T 11380 8720 5 5 1 1 0 6 1
pinnumber=26
T 11420 8720 5 5 1 1 0 0 1
pinlabel=PB2/DATA2/ADDR2
}
P 11300 8800 11400 8800 1 0 0
{
T 11150 8820 5 5 0 1 0 0 1
pinseq=27
T 11050 8820 5 5 0 1 0 0 1
pintype=io
T 11380 8820 5 5 1 1 0 6 1
pinnumber=27
T 11420 8820 5 5 1 1 0 0 1
pinlabel=PB3/DATA3/ADDR3
}
P 11300 8900 11400 8900 1 0 0
{
T 11150 8920 5 5 0 1 0 0 1
pinseq=28
T 11050 8920 5 5 0 1 0 0 1
pintype=io
T 11380 8920 5 5 1 1 0 6 1
pinnumber=28
T 11420 8920 5 5 1 1 0 0 1
pinlabel=PB4/DATA4/ADDR4
}
P 11300 9000 11400 9000 1 0 0
{
T 11150 9020 5 5 0 1 0 0 1
pinseq=29
T 11050 9020 5 5 0 1 0 0 1
pintype=io
T 11380 9020 5 5 1 1 0 6 1
pinnumber=29
T 11420 9020 5 5 1 1 0 0 1
pinlabel=PB5/DATA5/ADDR5
}
P 11300 9100 11400 9100 1 0 0
{
T 11150 9120 5 5 0 1 0 0 1
pinseq=30
T 11050 9120 5 5 0 1 0 0 1
pintype=io
T 11380 9120 5 5 1 1 0 6 1
pinnumber=30
T 11420 9120 5 5 1 1 0 0 1
pinlabel=PB6/DATA6/ADDR6
}
P 11300 9200 11400 9200 1 0 0
{
T 11150 9220 5 5 0 1 0 0 1
pinseq=31
T 11050 9220 5 5 0 1 0 0 1
pintype=io
T 11380 9220 5 5 1 1 0 6 1
pinnumber=31
T 11420 9220 5 5 1 1 0 0 1
pinlabel=PB7/DATA7/ADDR7
}
P 11300 9400 11400 9400 1 0 0
{
T 11150 9420 5 5 0 1 0 0 1
pinseq=57
T 11050 9420 5 5 0 1 0 0 1
pintype=io
T 11380 9420 5 5 1 1 0 6 1
pinnumber=57
T 11420 9420 5 5 1 1 0 0 1
pinlabel=PA0/DATA8/ADDR8
}
P 11300 9500 11400 9500 1 0 0
{
T 11150 9520 5 5 0 1 0 0 1
pinseq=58
T 11050 9520 5 5 0 1 0 0 1
pintype=io
T 11380 9520 5 5 1 1 0 6 1
pinnumber=58
T 11420 9520 5 5 1 1 0 0 1
pinlabel=PA1/DATA9/ADDR9
}
P 11300 9600 11400 9600 1 0 0
{
T 11150 9620 5 5 0 1 0 0 1
pinseq=59
T 11050 9620 5 5 0 1 0 0 1
pintype=io
T 11380 9620 5 5 1 1 0 6 1
pinnumber=59
T 11420 9620 5 5 1 1 0 0 1
pinlabel=PA2/DATA10/ADDR10
}
P 11300 9700 11400 9700 1 0 0
{
T 11150 9720 5 5 0 1 0 0 1
pinseq=60
T 11050 9720 5 5 0 1 0 0 1
pintype=io
T 11380 9720 5 5 1 1 0 6 1
pinnumber=60
T 11420 9720 5 5 1 1 0 0 1
pinlabel=PA3/DATA11/ADDR11
}
P 11300 9800 11400 9800 1 0 0
{
T 11150 9820 5 5 0 1 0 0 1
pinseq=61
T 11050 9820 5 5 0 1 0 0 1
pintype=io
T 11380 9820 5 5 1 1 0 6 1
pinnumber=61
T 11420 9820 5 5 1 1 0 0 1
pinlabel=PA4/DATA12/ADDR12
}
P 11300 9900 11400 9900 1 0 0
{
T 11150 9920 5 5 0 1 0 0 1
pinseq=62
T 11050 9920 5 5 0 1 0 0 1
pintype=io
T 11380 9920 5 5 1 1 0 6 1
pinnumber=62
T 11420 9920 5 5 1 1 0 0 1
pinlabel=PA5/DATA13/ADDR13
}
P 11300 10000 11400 10000 1 0 0
{
T 11150 10020 5 5 0 1 0 0 1
pinseq=63
T 11050 10020 5 5 0 1 0 0 1
pintype=io
T 11380 10020 5 5 1 1 0 6 1
pinnumber=63
T 11420 10020 5 5 1 1 0 0 1
pinlabel=PA6/DATA14/ADDR14
}
P 11300 10100 11400 10100 1 0 0
{
T 11150 10120 5 5 0 1 0 0 1
pinseq=64
T 11050 10120 5 5 0 1 0 0 1
pintype=io
T 11380 10120 5 5 1 1 0 6 1
pinnumber=64
T 11420 10120 5 5 1 1 0 0 1
pinlabel=PA7/DATA15/ADDR15
}
P 11300 10300 11400 10300 1 0 0
{
T 11150 10320 5 5 0 1 0 0 1
pinseq=48
T 11050 10320 5 5 0 1 0 0 1
pintype=io
T 11380 10320 5 5 1 1 0 6 1
pinnumber=48
T 11420 10320 5 5 1 1 0 0 1
pinlabel=TEST
}
P 11300 10500 11400 10500 1 0 0
{
T 11150 10520 5 5 0 1 0 0 1
pinseq=56
T 11050 10520 5 5 0 1 0 0 1
pintype=io
T 11380 10520 5 5 1 1 0 6 1
pinnumber=56
T 11420 10520 5 5 1 1 0 0 1
pinlabel=PE0/XIRQ*
}
P 11300 10600 11400 10600 1 0 0
{
T 11150 10620 5 5 0 1 0 0 1
pinseq=55
T 11050 10620 5 5 0 1 0 0 1
pintype=io
T 11380 10620 5 5 1 1 0 6 1
pinnumber=55
T 11420 10620 5 5 1 1 0 0 1
pinlabel=PE1/IRQ*
}
P 11300 10700 11400 10700 1 0 0
{
T 11150 10720 5 5 0 1 0 0 1
pinseq=54
T 11050 10720 5 5 0 1 0 0 1
pintype=io
T 11380 10720 5 5 1 1 0 6 1
pinnumber=54
T 11420 10720 5 5 1 1 0 0 1
pinlabel=PE2/R/W*
}
P 11300 10800 11400 10800 1 0 0
{
T 11150 10820 5 5 0 1 0 0 1
pinseq=53
T 11050 10820 5 5 0 1 0 0 1
pintype=io
T 11380 10820 5 5 1 1 0 6 1
pinnumber=53
T 11420 10820 5 5 1 1 0 0 1
pinlabel=PE3/TAGLO/LSTRB
}
P 11300 10900 11400 10900 1 0 0
{
T 11150 10920 5 5 0 1 0 0 1
pinseq=39
T 11050 10920 5 5 0 1 0 0 1
pintype=io
T 11380 10920 5 5 1 1 0 6 1
pinnumber=39
T 11420 10920 5 5 1 1 0 0 1
pinlabel=PE4/ECLK
}
P 11300 11000 11400 11000 1 0 0
{
T 11150 11020 5 5 0 1 0 0 1
pinseq=38
T 11050 11020 5 5 0 1 0 0 1
pintype=io
T 11380 11020 5 5 1 1 0 6 1
pinnumber=38
T 11420 11020 5 5 1 1 0 0 1
pinlabel=PE5/IPIPE0/MODA
}
P 11300 11100 11400 11100 1 0 0
{
T 11150 11120 5 5 0 1 0 0 1
pinseq=37
T 11050 11120 5 5 0 1 0 0 1
pintype=io
T 11380 11120 5 5 1 1 0 6 1
pinnumber=37
T 11420 11120 5 5 1 1 0 0 1
pinlabel=PE6/IPIPE1/MODB
}
P 11300 11200 11400 11200 1 0 0
{
T 11150 11220 5 5 0 1 0 0 1
pinseq=36
T 11050 11220 5 5 0 1 0 0 1
pintype=io
T 11380 11220 5 5 1 1 0 6 1
pinnumber=36
T 11420 11220 5 5 1 1 0 0 1
pinlabel=PE7/NOACC/XCLKS*
}
P 11300 11400 11400 11400 1 0 0
{
T 11150 11420 5 5 0 1 0 0 1
pinseq=42
T 11050 11420 5 5 0 1 0 0 1
pintype=io
T 11380 11420 5 5 1 1 0 6 1
pinnumber=42
T 11420 11420 5 5 1 1 0 0 1
pinlabel=RESET*
}
P 11300 11600 11400 11600 1 0 0
{
T 11150 11620 5 5 0 1 0 0 1
pinseq=47
T 10950 11620 5 5 0 1 0 0 1
pintype=pas
T 11380 11620 5 5 1 1 0 6 1
pinnumber=47
T 11420 11620 5 5 1 1 0 0 1
pinlabel=XTAL
}
P 11300 11700 11400 11700 1 0 0
{
T 11150 11720 5 5 0 1 0 0 1
pinseq=46
T 10950 11720 5 5 0 1 0 0 1
pintype=pas
T 11380 11720 5 5 1 1 0 6 1
pinnumber=46
T 11420 11720 5 5 1 1 0 0 1
pinlabel=EXTAL
}
P 11300 11900 11400 11900 1 0 0
{
T 11150 11920 5 5 0 1 0 0 1
pinseq=44
T 11050 11920 5 5 0 1 0 0 1
pintype=io
T 11380 11920 5 5 1 1 0 6 1
pinnumber=44
T 11420 11920 5 5 1 1 0 0 1
pinlabel=XFC
}
P 11300 12100 11400 12100 1 0 0
{
T 11150 12120 5 5 0 1 0 0 1
pinseq=23
T 11050 12120 5 5 0 1 0 0 1
pintype=io
T 11380 12120 5 5 1 1 0 6 1
pinnumber=23
T 11420 12120 5 5 1 1 0 0 1
pinlabel=BKGD/TAGHI*/MODC
}
L 11400 12200 14200 12200 3 0 0 0 -1 -1
P 11300 6700 11400 6700 1 0 0
{
T 11150 6720 5 5 0 1 0 0 1
pinseq=67
T 11050 6720 5 5 0 1 0 0 1
pintype=io
T 11380 6720 5 5 1 1 0 6 1
pinnumber=67
T 11420 6720 5 5 1 1 0 0 1
pinlabel=PAD00/AN00
}
P 11300 6800 11400 6800 1 0 0
{
T 11150 6820 5 5 0 1 0 0 1
pinseq=69
T 11050 6820 5 5 0 1 0 0 1
pintype=io
T 11380 6820 5 5 1 1 0 6 1
pinnumber=69
T 11420 6820 5 5 1 1 0 0 1
pinlabel=PAD01/AN01
}
P 11300 6900 11400 6900 1 0 0
{
T 11150 6920 5 5 0 1 0 0 1
pinseq=71
T 11050 6920 5 5 0 1 0 0 1
pintype=io
T 11380 6920 5 5 1 1 0 6 1
pinnumber=71
T 11420 6920 5 5 1 1 0 0 1
pinlabel=PAD02/AN02
}
P 11300 7000 11400 7000 1 0 0
{
T 11150 7020 5 5 0 1 0 0 1
pinseq=73
T 11050 7020 5 5 0 1 0 0 1
pintype=io
T 11380 7020 5 5 1 1 0 6 1
pinnumber=73
T 11420 7020 5 5 1 1 0 0 1
pinlabel=PAD03/AN03
}
P 11300 7100 11400 7100 1 0 0
{
T 11150 7120 5 5 0 1 0 0 1
pinseq=75
T 11050 7120 5 5 0 1 0 0 1
pintype=io
T 11380 7120 5 5 1 1 0 6 1
pinnumber=75
T 11420 7120 5 5 1 1 0 0 1
pinlabel=PAD04/AN04
}
P 11300 7200 11400 7200 1 0 0
{
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SPI1
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PWM
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CANbus
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SCI
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SPI0
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{
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TQFP75P22K22-112N-AFA
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C 17000 11400 1 0 0 EMBEDDEDheader_100mil_2x13_male_vert_shrouded-1.sym
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C 16650 6300 1 0 0 EMBEDDEDheader_100mil_2x13_male_vert_shrouded-1.sym
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C 15700 4300 1 0 0 EMBEDDEDheader_100mil_2x13_male_vert_shrouded-1.sym
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C 6300 12400 1 180 0 EMBEDDEDheader_100mil_2x13_male_vert_shrouded-1.sym
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C 6300 9800 1 180 0 EMBEDDEDheader_100mil_2x13_male_vert_shrouded-1.sym
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{
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V 5750 9700 31 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 5720 9700 5700 9700 3 0 0 0 -1 -1
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{
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device=header_100mil_2x13_male_vert_shrouded
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T 4600 -619300 5 5 0 0 180 0 1
footprint=header_2.54mm_2x13_male_vert_ribbonshroud
T 4600 -619400 5 5 0 0 180 0 1
license=http://www.freelabs.com/~whitis/software/license.html
T 4600 -619500 5 5 0 0 180 0 1
documentation=http://rocky.digikey.com/WebLib/3M/Web%20Data/2500%20Series.pdf
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C 5100 8900 1 180 0 EMBEDDEDheader_100mil_2x13_male_vert_shrouded-1.sym
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